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The world’s needs for analyzing massive amounts of data is growing dramatically. The computation demands of these abundant-data applications, such as AI, far exceed the capabilities of today’s computing systems and cannot be met with isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. We must create new transformative NanoSystems which exploit salient properties of underlying nanotechnologies to implement 21st century architectures. 

Our N3XT (Nano-Engineered Computing Systems Technology) project creates 21st century NanoSystems through new computation-immersed-in-memory architectures that integrate new logic and memory nanotechnologies in dense 3D. Such architectures are made possible by new logic devices (such as carbon nanotube transistors for high-speed and low-energy circuits) and high-density non-volatile memory (such as resistive RAM that can store multiple bits inside each memory cell) that are amenable to ultra-dense (monolithic) 3D integration of thin layers of logic and memory.

A wide variety of N3XT hardware prototypes (built in commercial and research facilities) represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual NanoSystems. N3XT NanoSystems target 1,000X system-level energy-delay-product benefits especially for abundant-data applications. Such massive benefits enable coming generations of applications that push new frontiers, from deeply-embedded computing systems all the way to the cloud.

Related Publications

  • Srimani, T, A. C. Yu, R. Radway, D. Rich, M. Nelson, S. Wong, D. Murphy, S. Fuller, G. Hills, S. Mitra, M.M. Shulaker. “Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM”, IEEE Symp. VLSI Tech, 2023 (to appear)
  • Rich, Dennis, Anna Kasperovich, Mohamadali Molakoutian, Robert Radway, Shiho Hagiwara, Takahide Yoshikawa, Srabanti Chowdhury, Subhasish Mitra, “Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits”, IEEE/ACM Design Automation Conference, 2023 (to appear)
  • Srimani, Tathagata*, Robert Radway*, Jinwoo Kim*, Kartik Prabhu, Dennis Rich, Carlo Gilardi, Priyanka Raina, Max Shulaker, Sung-Kyu Lim, Subhasish Mitra, “Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits”, IEEE/ACM Design Automation Test Exhibition, April 2023
  • K. Prabhu, A. Gural, Z. F. Khan, R. M. Radway, M. Giordano, K. Koul, R. Doshi, J. W. Kustin, T. Liu, G. B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," in IEEE Journal of Solid-State Circuits, vol. 57, no. 4, pp. 1013-1026, April 2022
  • Q. Lin, G. Pitner, C. Gilardi, S.-K. Su, Z. Zhang, E. Chen, P. Bandaru, A. Kummel, H. Wang, M. Passlack, S. Mitra, and H.-S. P. Wong, "Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs," in IEEE Electron Device Letters, vol. 43, no. 3, pp. 490-493, March 2022
  • R. M. Radway, K. Sethi, W.-C. Chen, J. Kwon, S. Liu, T. F. Wu, E. Beigne, M. M. Shulaker,  H.-S. P. Wong, and S. Mitra, "The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design," IEEE International Electron Devices Meeting, Dec. 2021 (invited)
  • C. Gilardi, B. Chehab, G. Sisto, P. Schuddinck, Z. Ahmed, O. Zografos, Q. Lin, G. Hellings, J. Ryckaert, H.-S. P. Wong, and S. Mitra, "Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization," IEEE International Electron Devices Meeting, Dec. 2021
  • M. Giordano, K. Prabhu, K. Koul, R. M. Radway, A. Gural, R. Doshi, Z. F. Khan, J. W. Kustin, T. Liu, G. B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," Symposium on VLSI Circuits, 2021, pp. 1-2.
  • R. Radway, A. Bartolo, P. Jolly, Z. Khan, B. Le, P. Tandon, T. Wu, Y. Xin, E. Vianello, P. Vivet, E. Nowak, H.-S.P. Wong, M. Sabry Aly, E. Beigne, M. Wootters and S. Mitra, “Illusion of Large On-Chip Memory by Networked Computing Chips for Neural Network Inference,” Nature Electronics, Jan. 2021.
  • G. Pitner, Z. Zhang, Q. Lin, S.-K Su, C. Gilardi, C. Kuo, H. Kashyap, T. Weiss, Z. Yu, T.-A. Chao, L.-J. Li, S. Mitra, H.-S. P. Wong, J. Cai, A. Kummel, P. Bandaru and M. Passlack, “Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length,” IEEE Intl. Electron Devices Meeting, Dec. 2020.
  • E. Esmanhotto, L. Brunet, N. Castellani, D. Bonnet, T. Dalgaty, L. Grenouillet, D. Ly, C. Cagli, C. Vizioz, N. Allouti, F. Laulagnet, O. Gully, N. Bernard-Henriques, M. Bocquet, G. Molas, P. Vivet, D. Querlioz, JM. Portal, S. Mitra, F. Andrieu, C. Fenouillet-Beranger, E. Nowak and E. Vianello, “High-Density 3D Monolithically Stacked 1T1R Multi-Level-Cell for Neural Networks,” IEEE Intl. Electron Devices Meeting, Dec. 2020.
  • H.-S.P. Wong, K. Akarvardar, D. Antoniadis, J. Bokor, C. Hu, T.-J. King-Liu, S. Mitra, J. Plummer and S. Salahuddin, “A Density Metric for Semiconductor Technology,” Proceedings of the IEEE, April 2020.
  • E.R. Hsieh, M. Giordano, B. Hodson, A. Levy, S.K. Osekowsky, R.M. Radway, Y.C. Shih, W. Wan, T.F. Wu, X. Zheng, M. Nelson, B.Q. Le, H.-S.P. Wong, S. Mitra and S. Wong, “High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2019.
  • M. Bishop, H.-S.P. Wong, S. Mitra and M. Shulaker, “Monolithic Three-Dimensional Integration,” IEEE Micro, Special Issue on Monolithic 3D Integration, Dec. 2019.
  • T. Wu, B. Le, R. Radway, A. Bartolo, W. Hwang, S. Jeong, H. Li, P. Tandon, E. Vianello, P. Vivet, E. Nowak, M. Wootters, H.-S.P. Wong, M. Aly, E. Beigne and S. Mitra, “A 43pJ/cycle Non-volatile Microcontroller with 4.7µs Shutdown/Wake-up integrating 2.3 bits-per-cell Resistive RAM and Resilience Techniques,” IEEE Intl. Solid-State Circuits Conf., San Francisco, CA, Feb. 2019.
  • B. Le, A. Grossi, E. Vianello, T. Wu, G. Lama, E. Beigne, H.-S.P. Wong and S. Mitra, “Resistive RAM with Multiple Bits per Cell: Array-Level Demonstration of 3 Bits per Cell,” IEEE Trans. Electron Devices, Feb. 2019 (Special Research Highlight by Nature Electronics).
  • M. Aly, T.F. Wu, A. Bartolo, Y. Malviya, W. Hwang, G. Hills, I. Markov, M. Wootters, M. Shulaker, H.-S.P. Wong and S. Mitra, “The N3XT Approach to Energy-Efficient Abundant-Data Computing,” Proceedings of the IEEE, Special Issue on Nonsilicon, Non-von Neumann Computing, Jan. 2019 (Invited, Cover Feature).
  • T. Wu, P.-C. Huang, A. Rahimi, H. Li, M. Shulaker, J. Rabaey, H.-S.P. Wong and S. Mitra, “Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study,” IEEE Intl. Solid-State Circuits Conf., San Francisco, CA, Feb. 2018.
  • M. Shulaker, G. Hills, R. Park, R.T. Howe, K. Saraswat, H.-S.P. Wong and S. Mitra, “Three-dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip,” Nature, 2017 (Special News and Views feature by Nature).
  • M. Aly, M. Gao, G. Hills, C-S Lee, G. Pitner, M. Shulaker, T. Wu, M. Asheghi, J. Bokor, F. Franchetti, K. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Ré, H.-S.P. Wong and S. Mitra, “Energy-Efficient Abundant-Data Computing: The N3XT 1,000X,” IEEE Computer, Special Issue on Rebooting Computing, Dec. 2015.